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High Performance E2CMOS(R) In-System Programmable Logic FEATURES
x High-performance, E2CMOS 3.3-V & 5-V CPLD families x Flexible architecture for rapid logic designs
MACH 4 CPLD Family
x
x x x
x
x x
x
-- Excellent First-Time-FitTM and refit feature -- SpeedLockingTM performance for guaranteed fixed timing -- Central, input and output switch matrices for 100% routability and 100% pin-out retention High speed -- 7.5ns tPD Commercial and 10ns tPD Industrial -- 111.1MHz fCNT 32 to 256 macrocells; 32 to 384 registers 44 to 256 pins in PLCC, PQFP, TQFP and BGA packages Flexible architecture for a wide range of design styles -- D/T registers and latches -- Synchronous or asynchronous mode -- Dedicated input registers -- Programmable polarity -- Reset/ preset swapping Advanced capabilities for easy system integration -- 3.3-V & 5-V JEDEC-compliant operations -- JTAG (IEEE 1149.1) compliant for boundary scan testing -- 3.3-V & 5-V JTAG in-system programming -- PCI compliant (-7/-10/-12 speed grades) -- Safe for mixed supply voltage system designs -- Bus-FriendlyTM inputs and I/Os -- Programmable security bit -- Individual output slew rate control Advanced E2CMOS process provides high-performance, cost-effective solutions Supported by ispDesignEXPERTTM software for rapid logic development -- Supports HDL design methodologies with results optimized for MACH 4 -- Flexibility to adapt to user requirements -- Software partnerships that ensure customer success Lattice and third-party hardware programming support -- LatticePROTM software for in-system programmability support on PCs and automated test equipment -- Programming support on all major programmers including Data I/O, BP Microsystems, Advin, and System General
Publication# 17466 Amendment/0
Rev: M Issue Date: March 2000
Table 1. MACH 4 Device Features1, 2
Feature Macrocells Maximum User I/O Pins tPD (ns) fCNT (MHz) tCOS (ns) tSS (ns) Static Power (mA) JTAG Compliant PCI Compliant M4-32/32 M4LV-32/32 32 32 7.5 111 5.5 5.5 25 Yes Yes M4-64/32 M4LV-64/32 64 32 7.5 111 5.5 5.5 25 Yes Yes M4-96/48 M4LV-96/48 96 48 7.5 111 5.5 5.5 50 Yes Yes M4-128/64 M4LV-128/64 128 64 7.5 111 5.5 5.5 70 Yes Yes M4-128N/64 M4LV-128N/64 128 64 7.5 111 5.5 5.5 70 No Yes M4-192/96 M4LV-192/96 192 96 7.5 111 5.5 5.5 85 Yes Yes M4-256/128 M4LV-256/128 256 128 7.5 111 5.5 5.5 100 Yes Yes
Notes: 1. For information on the M4-96/96 device, please refer to the M4-96/96 data sheet at www.latticesemi.com. 2. "M4-xxx" is for 5-V devices. "M4LV-xxx" is for 3.3-V devices.
2
MACH 4 Family
GENERAL DESCRIPTION
The MACH(R) 4 family from Lattice offers an exceptionally flexible architecture and delivers a superior Complex Programmable Logic Device (CPLD) solution of easy-to-use silicon products and software tools. The overall benefits for users are a guaranteed and predictable CPLD solution, faster time-to-market, greater flexibility and lower cost. The MACH 4 devices offer densities ranging from 32 to 256 macrocells with 100% utilization and 100% pin-out retention. The MACH 4 family offer 5-V (M4-xxx) and 3.3-V (M4LV-xxx) operation. MACH 4 products are 5-V or 3.3-V in-system programmable through the JTAG (IEEE Std. 1149.1) interface. JTAG boundary scan testing also allows product testability on automated test equipment for device connectivity. All MACH 4 family members deliver First-Time-Fit and easy system integration with pin-out retention after any design change and refit. For both 3.3-V and 5-V operation, MACH 4 products can deliver guaranteed fixed timing as fast as 7.5 ns tPD and 111 MHz fCNT through the SpeedLocking feature when using up to 20 product terms per output (Table 2).
Table 2. MACH 4 Speed Grades
Speed Grade1 Device M4-32/32 M4LV-32/32 M4-64/32 M4LV-64/32 M4-96/48 M4LV-96/48 M4-128/64 M4LV-128/64 M4-128N/64 M4LV-128N/64 M4-192/96 M4LV-192/96 M4-256/128 M4LV-256/128 Note: 1. C = Commercial, -7 C C C C C C C -10 C, I C, I C, I C, I C, I C, I C, I -12 C, I C, I C, I C, I C, I C, I C, I -14 I I I I I I I -15 C C C C C C C -18 I I I I I I I
I = Industrial
The MACH 4 family offers numerous density-I/O combinations in Thin Quad Flat Pack (TQFP), Plastic Quad Flat Pack (PQFP), Plastic Leaded Chip Carrier (PLCC), and Ball Grid Array (BGA) packages ranging from 44 to 256 pins (Table 3). It also offers I/O safety features for mixedvoltage designs so that the 3.3-V devices can accept 5-V inputs, and 5-V devices do not overdrive 3.3-V inputs. Additional features include Bus-Friendly inputs and I/Os, a programmable powerdown mode for extra power savings and individual output slew rate control for the highest speed transition or for the lowest noise transition.
MACH 4 Family
3
Table 3. MACH 4 Package and I/O Options (Number of I/Os and dedicated inputs in Table)
Package 44-pin PLCC 44-pin TQFP 48-pin TQFP 84-pin PLCC 100-pin TQFP 100-pin PQFP 144-pin TQFP 208-pin PQFP 256-ball BGA 48+8 64+6 64+6 96+16 128+14 128+14 M4-32/32 M4LV-32/32 32+2 32+2 32+2 M4-64/32 M4LV-64/32 32+2 32+2 32+2 64+6 M4-96/48 M4LV-96/48 M4-128/64 M4LV-128/64 M4-128N/64 M4LV-128N/64 M4-192/96 M4LV-192/96 M4-256/128 M4LV-256/128
4
MACH 4 Family
FUNCTIONAL DESCRIPTION
The fundamental architecture of MACH 4 devices (Figure 1) consists of multiple, optimized PAL(R) blocks interconnected by a central switch matrix. The central switch matrix allows communication between PAL blocks and routes inputs to the PAL blocks. Together, the PAL blocks and central switch matrix allow the logic designer to create large designs in a single device instead of having to use multiple devices. The key to being able to make effective use of these devices lies in the interconnect schemes. In MACH 4 architecture, the macrocells are flexibly coupled to the product terms through the logic allocator, and the I/O pins are flexibly coupled to the macrocells due to the output switch matrix. In addition, more input routing options are provided by the input switch matrix. These resources provide the flexibility needed to fit designs efficiently.
PAL Block 4 Clock Generator Clock/Input Pins
Note 3 Note 2
Central Switch Matrix
Logic Array Input Switch Matrix
Logic 16 Output/ Allocator Buried with XOR Macrocells 16
16
8
Note 1
Dedicated Input Pins
16 PAL Block PAL Block
I/O Cells
33/ 34/ 36
Output Switch Matrix
I/O Pins
I/O Pins
I/O Pins
17466G-001
Figure 1. MACH 4 Block Diagram and PAL Block Structure
Notes: 1. 16 for MACH 4 devices with 1:1 macrocell-I/O cell ratio (see next page). 2. Block clocks do not go to I/O cells in M4(LV)-32/32. 3. M4(LV)-192/96 and M4(LV)-256/128 have dedicated clock pins which cannot be used as inputs and do not connect to the central switch matrix.
MACH 4 Family
5
Table 4. Architectural Summary of MACH 4 devices
MACH 4 Devices M4-64/32, M4LV-64/32 M4-96/48, M4LV-96/48 M4-128/64, M4LV-128/64 M4-128N/64, M4LV-128N/64 M4-192/96, M4LV-192/96 M4-256/128, M4LV-256/128 Macrocell-I/O Cell Ratio Input Switch Matrix Input Registers Central Switch Matrix Output Switch Matrix 2:1 Yes Yes Yes Yes
M4-32/32 M4LV-32/32
1:1 Yes No Yes Yes
The Macrocell-I/O cell ratio is defined as the number of macrocells versus the number of I/O cells internally in a PAL block (Table 4). The central switch matrix takes all dedicated inputs and signals from the input switch matrices and routes them as needed to the PAL blocks. Feedback signals that return to the same PAL block still must go through the central switch matrix. This mechanism ensures that PAL blocks in MACH 4 devices communicate with each other with consistent, predictable delays. The central switch matrix makes a MACH 4 device more advanced than simply several PAL devices on a single chip. It allows the designer to think of the device not as a collection of blocks, but as a single programmable device; the software partitions the design into PAL blocks through the central switch matrix so that the designer does not have to be concerned with the internal architecture of the device. Each PAL block consists of:
x x x x x x x
Product-term array Logic allocator Macrocells Output switch matrix I/O cells Input switch matrix Clock generator
6
MACH 4 Family
Product-Term Array The product-term array consists of a number of product terms that form the basis of the logic being implemented. The inputs to the AND gates come from the central switch matrix (Table 5), and are provided in both true and complement forms for efficient logic implementation.
Table 5. PAL Block Inputs
Device M4-32/32 and M4LV-32/32 M4-64/32 and M4LV-64/32 M4-96/48 and M4LV-96/48 M4-128/64 and M4LV-128/64 M4-128N/64 and M4LV-128N/64 M4-192/96 and M4LV-192/96 M4-256/128 and M4LV-256/128 Number of Inputs to PAL Block 33 33 33 33 33 34 34
Logic Allocator Within the logic allocator, product terms are allocated to macrocells in "product term clusters." The availability and distribution of product term clusters are automatically considered by the software as it fits functions within a PAL block. The size of a product term cluster has been optimized to provide high utilization of product terms, making complex functions using many product terms possible. Yet when few product terms are used, there will be a minimal number of unused--or wasted--product terms left over. The product term clusters available to each macrocell within a PAL block are shown in Tables 6 and 7. Each product term cluster is associated with a macrocell. The size of a cluster depends on the configuration of the associated macrocell. When the macrocell is used in synchronous mode (Figure 2a), the basic cluster has 4 product terms. When the associated macrocell is used in asynchronous mode (Figure 2b), the cluster has 2 product terms. Note that if the product term cluster is routed to a different macrocell, the allocator configuration is not determined by the mode of the macrocell actually being driven. The configuration is always set by the mode of the macrocell that the cluster will drive if not routed away, regardless of the actual routing. In addition, there is an extra product term that can either join the basic cluster to give an extended cluster, or drive the second input of an exclusive-OR gate in the signal path. If included with the basic cluster, this provides for up to 20 product terms on a synchronous function that uses four extended 5-product-term clusters. A similar asynchronous function can have up to 18 product terms. When the extra product term is used to extend the cluster, the value of the second XOR input can be programmed as a 0 or a 1, giving polarity control. The possible configurations of the logic allocator are shown in Figures 3 and 4.
MACH 4 Family
7
Table 6. Logic Allocator for All MACH 4 Devices (except M4(LV)-32/32)
Output Macrocell M0 M1 M2 M3 M4 M5 M6 M7 Available Clusters C0, C1, C2 C0, C1, C2, C3 C1, C2, C3, C4 C2, C3, C4, C5 C3, C4, C5, C6 C4, C5, C6, C7 C5, C6, C7, C8 C6, C7, C8, C9 Output Macrocell M8 M9 M10 M11 M12 M13 M14 M15 Available Clusters C7, C8, C9, C10 C8, C9, C10, C11 C9, C10, C11, C12 C10, C11, C12, C13 C11, C12, C13, C14 C12, C13, C14, C15 C13, C14, C15 C14, C15
Table 7. Logic Allocator for M4(LV)-32/32
Output Macrocell M0 M1 M2 M3 M4 M5 M6 M7 Available Clusters C0, C1, C2 C0, C1, C2, C3 C1, C2, C3, C4 C2, C3, C4, C5 C3, C4, C5, C6 C4, C5, C6, C7 C5, C6, C7 C6, C7
From n-1
Output Macrocell M8 M9 M10 M11 M12 M13 M14 M15
Available Clusters C8, C9, C10 C8, C9, C10, C11 C9, C10, C11, C12 C10, C11, C12, C13 C11, C12, C13, C14 C12, C13, C14, C15 C13, C14, C15 C14, C15
To n-1 To n-2
Logic Allocator
Basic Product Term Cluster
n
n 0 Default
To n+1 From n+1 From n+2
Extra Product Term
0 Default
Prog. Polarity
To Macrocell n
17466G-005
a. Synchronous Mode
From n-1 To n-1 To n-2
Logic Allocator
Basic Product Term Cluster
n
n 0 Default
Extra Product Term
0 Default
From n+1 From n+2
To n+1
Prog. Polarity
b. Asynchronous Mode
To Macrocell n
17466G-006
Figure 2. Logic Allocator: Configuration of Cluster "n" Set by Mode of Macrocell "n"
8
MACH 4 Family
a. Basic cluster with XOR
b. Extended cluster, active high
c. Extended cluster, active low
0
d. Basic cluster routed away; single-product-term, active high
e. Extended cluster routed away
17466G-007
Figure 3. Logic Allocator Configurations: Synchronous Mode
a. Basic cluster with XOR
b. Extended cluster, active high
c. Extended cluster, active low
0
d. Basic cluster routed away; single-product-term, active high
e. Extended cluster routed away
17466G-008
Figure 4. Logic Allocator Configurations: Asynchronous Mode
Note that the configuration of the logic allocator has absolutely no impact on the speed of the signal. All configurations have the same delay. This means that designers do not have to decide between optimizing resources or speed; both can be optimized. If not used in the cluster, the extra product term can act in conjunction with the basic cluster to provide XOR logic for such functions as data comparison, or it can work with the D-,T-type flipflop to provide for J-K, and S-R register operation. In addition, if the basic cluster is routed to another macrocell, the extra product term is still available for logic. In this case, the first XOR input will be a logic 0. This circuit has the flexibility to route product terms elsewhere without giving up the use of the macrocell. Product term clusters do not "wrap" around a PAL block. This means that the macrocells at the ends of the block have fewer product terms available.
MACH 4 Family
9
Macrocell The macrocell consists of a storage element, routing resources, a clock multiplexer, and initialization control. The macrocell has two fundamental modes: synchronous and asynchronous (Figure 5). The mode chosen only affects clocking and initialization in the macrocell.
Power-Up Reset
PAL-Block Initialization Product Terms
Common PAL-block resource Individual macrocell resources
SWAP
From Logic Allocator From PAL-Clock Generator
Block CLK0 Block CLK1 Block CLK2 Block CLK3
AP D/T/L
AR Q
To Output and Input Switch Matrices
17466G-009
a. Synchronous mode
Power-Up Reset Individual Initialization Product Term
From Logic Allocator From PAL-Block Clock Generator Individual Clock Product Term
Block CLK0 Block CLK1
AP AR D/T/L Q
To Output and Input Switch Matrices
b. Asynchronous mode
17466G-010
Figure 5. Macrocell
In either mode, a combinatorial path can be used. For combinatorial logic, the synchronous mode will generally be used, since it provides more product terms in the allocator.
10
MACH 4 Family
The flip-flop can be configured as a D-type or T-type latch. J-K or S-R registers can be synthesized. The primary flip-flop configurations are shown in Figure 6, although others are possible. Flip-flop functionality is defined in Table 8. Note that a J-K latch is inadvisable as it will cause oscillation if both J and K inputs are HIGH.
AP AR D Q AP AR D Q
a. D-type with XOR
b. D-type with programmable D polarity
L
AP AR Q
AP AR L Q
G
G
c. Latch with XOR
d. Latch with programmable D polarity
AP AR T Q
f. Combinatorial with XOR e. T-type with programmable T polarity
g. Combinatorial with programmable polarity
17466G-011
Figure 6. Primary Macrocell Configurations
MACH 4 Family
11
Table 8. Register/Latch Operation
Configuration D-type Register Input(s) D=X D=0 D=1 T=X T=0 T=1 D=X D=0 D=1 CLK/LE 1 0,1, () () () 0, 1, () () () 1(0) 0(1) 0(1) Q+ Q 0 1 Q Q Q Q 0 1
T-type Register
D-type Latch
Note: 1. Polarity of CLK/LE can be programmed
Although the macrocell shows only one input to the register, the XOR gate in the logic allocator allows the D-, T-type register to emulate J-K, and S-R behavior. In this case, the available product terms are divided between J and K (or S and R). When configured as J-K, S-R, or T-type, the extra product term must be used on the XOR gate input for flip-flop emulation. In any register type, the polarity of the inputs can be programmed. The clock input to the flip-flop can select any of the four PAL block clocks in synchronous mode, with the additional choice of either polarity of an individual product term clock in the asynchronous mode. The initialization circuit depends on the mode. In synchronous mode (Figure 7), asynchronous reset and preset are provided, each driven by a product term common to the entire PAL block.
Power-Up Reset PAL-Block Initialization Product Terms AP D/T/L AR Q Power-Up Preset PAL-Block Initialization Product Terms AP D/L AR Q
a. Power-up reset
17466G-012
b. Power-up preset
17466G-013
Figure 7. Synchronous Mode Initialization Configurations
12
MACH 4 Family
A reset/preset swapping feature in each macrocell allows for reset and preset to be exchanged, providing flexibility. In asynchronous mode (Figure 8), a single individual product term is provided for initialization. It can be selected to control reset or preset.
Power-Up Reset Individual Reset Product Term Individual Preset Product Term Power-Up Preset
AP D/L/T
AR Q
AP D/L/T
AR Q
a. Reset
17466G-014
b. Preset
17466G-015
Figure 8. Asynchronous Mode Initialization Configurations
Note that the reset/preset swapping selection feature effects power-up reset as well. The initialization functionality of the flip-flops is illustrated in Table 9. The macrocell sends its data to the output switch matrix and the input switch matrix. The output switch matrix can route this data to an output if so desired. The input switch matrix can send the signal back to the central switch matrix as feedback.
Table 9. Asynchronous Reset/Preset Operation
AR 0 0 1 1 Note: 1. Transparent latch is unaffected by AR, AP AP 0 1 0 1 CLK/LE1 X X X X Q+ See Table 8 1 0 0
MACH 4 Family
13
Output Switch Matrix The output switch matrix allows macrocells to be connected to any of several I/O cells within a PAL block. This provides high flexibility in determining pinout and allows design changes to occur without effecting pinout. In MACH 4 devices with 2:1 Macrocell-I/O cell ratio, each PAL block has twice as many macrocells as I/O cells. The MACH 4 output switch matrix allows for half of the macrocells to drive I/O cells within a PAL block, in combinations according to Figure 9. Each I/O cell can choose from eight macrocells; each macrocell has a choice of four I/O cells. The MACH 4 devices with 1:1 Macrocell-I/O cell ratio allow each macrocell to drive one of eight I/O cells (Figure 9).
M0 M1 M2 M3 M4 M5 macrocells M6 I/O cell MUX M7 M8 M9 M10 M11 M12 M13 M14 M15 Each I/O cell can choose one of 8 macrocells in all MACH 4 devices. Each macrocell can drive one of 4 I/O cells in MACH 4 devices with 2:1 macrocell-I/O cell ratio. I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7
M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15
I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15
Each macrocell can drive one of 8 I/O cells in M4(LV)-32/32 devices.
Figure 9. MACH 4 Output Switch Matrix
14
MACH 4 Family
Table 10. Output Switch Matrix Combinations for MACH 4 Devices with 2:1 Macrocell-I/O Cell Ratio
Macrocell M0, M1 M2, M3 M4, M5 M6, M7 M8, M9 M10, M11 M12, M13 M14, M15 I/O Cell I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 Routable to I/O Cells I/O0, I/O5, I/O6, I/O7 I/O0, I/O1, I/O6, I/O7 I/O0, I/O1, I/O2, I/O7 I/O0, I/O1, I/O2, I/O3 I/O1, I/O2, I/O3, I/O4 I/O2, I/O3, I/O4, I/O5 I/O3, I/O4, I/O5, I/O6 I/O4, I/O5, I/O6, I/O7 Available Macrocells M0, M1, M2, M3, M4, M5, M6, M7 M2, M3, M4, M5, M6, M7, M8, M9 M4, M5, M6, M7, M8, M9, M10, M11 M6, M7, M8, M9, M10, M11, M12, M13 M8, M9, M10, M11, M12, M13, M14, M15 M0, M1, M10, M11, M12, M13, M14, M15 M0, M1, M2, M3, M12, M13, M14, M15 M0, M1, M2, M3, M4, M5, M14, M15
Table 11. Output Switch Matrix Combinations for M4(LV)-32/32
Macrocell M0, M1, M2, M3, M4, M5, M6, M7 M8, M9, M10, M11, M12, M13, M14, M15 I/O Cell I/O0, I/O1, I/O2, I/O3, I/O4, I/O5, I/O6, I/O7 I/O8, I/O9, I/O10, I/O11, I/O12, I/O13, I/O14, I/O15 Routable to I/O Cells I/O0, I/O1, I/O2, I/O3, I/O4, I/O5, I/O6, I/O7 I/O8, I/O9, I/O10, I/O11, I/O12, I/O13, I/O14, I/O15 Available Macrocells M0, M1, M2, M3, M4, M5, M6, M7 M8, M9, M10, M11, M12, M13, M14, M15
MACH 4 Family
15
I/O Cell The I/O cell (Figures 10 and 11) simply consists of a programmable output enable, a feedback path, and flip-flop (except MACH 4 devices with 1:1 macrocell-I/O cell ratio.) An individual output enable product term is provided for each I/O cell. The feedback signal drives the input switch matrix.
Individual Output Enable Product Term From Output Switch Matrix Individual Output Enable Product Term From Output Switch Matrix
To Input Switch Matrix
Q D/L
Block CLK0 Block CLK1 Block CLK2 Block CLK3 Power-up reset
17466G-017 17466G-018
To Input Switch Matrix
Figure 10. I/O Cell for MACH 4 Devices with 2:1 Macrocell-I/O Cell Ratio
Figure 11. I/O Cell for MACH 4 Devices with 1:1 Macrocell-I/O Cell Ratio
The I/O cell (Figure 10) contains a flip-flop, which provides the capability for storing the input in a D-type register or latch. The clock can be any of the PAL block clocks. Both the direct and registered versions of the input are sent to the input switch matrix. This allows for such functions as "time-domain-multiplexed" data comparison, where the first data value is stored, and then the second data value is put on the I/O pin and compared with the previous stored value. Note that the flip-flop used in the MACH 4 I/O cell is independent of the flip-flops in the macrocells. It powers up to a logic low.
Zero-Hold-Time Input Register
The MACH 4 devices have a zero-hold-time (ZHT) fuse which controls the time delay associated with loading data into all I/O cell registers and latches. When programmed, the ZHT fuse increases the data path setup delays to input storage elements, matching equivalent delays in the clock path. When the fuse is erased, the setup time to the input storage element is minimized. This feature facilitates doing worst-case designs for which data is loaded from sources which have low (or zero) minimum output propagation delays from clock edges. Input Switch Matrix The input switch matrix (Figures 12 and 13) optimizes routing of inputs to the central switch matrix. Without the input switch matrix, each input and feedback signal has only one way to enter the central switch matrix. The input switch matrix provides additional ways for these signals to enter the central switch matrix.
16
MACH 4 Family
From Input Cell
From Macrocell 1
From Macrocell 2
Direct
Registered/Latched
To Central Switch Matrix
17466G-002
To Central Switch Matrix
Figure 12. MACH 4 with 2:1 Macrocell-I/O Cell Ratio - Input Switch Matrix
Figure 13. MACH 4 with 1:1 Macrocell-I/O Cell Ratio - Input Switch Matrix
PAL Block Clock Generation Each MACH 4 device has four clock pins that can also be used as inputs. These pins drive a clock generator in each PAL block (Figure 14). The clock generator provides four clock signals that can be used anywhere in the PAL block. These four PAL block clock signals can consist of a large number of combinations of the true and complement edges of the global clock signals. Table 12 lists the possible combinations.
GCLK0 Block CLK0 (GCLK0 or GCLK1) GCLK1 Block CLK1 (GCLK1 or GCLK0) Block CLK2 (GCLK2 or GCLK3) Block CLK3 (GCLK3 or GCLK2)
GCLK2
GCLK3
From Macrocell
17466G-003
17466G-004
Figure 14. PAL Block Clock Generator 1
Note: 1. M4(LV)-32/32 and M4(LV)-64/32 have only two clock pins, GCLK0 and GCLK1. GCLK2 is tied to GCLK0, and GCLK3 is tied to GCLK1.
MACH 4 Family
From I/O Pin
17
Table 12. PAL Block Clock Combinations1
Block CLK0 GCLK0 GCLK1 GCLK0 GCLK1 X X X X Block CLK1 GCLK1 GCLK1 GCLK0 GCLK0 X X X X Block CLK2 X X X X GCLK2 (GCLK0) GCLK3 (GCLK1) GCLK2 (GCLK0) GCLK3 (GCLK1) Block CLK3 X X X X GCLK3 (GCLK1) GCLK3 (GCLK1) GCLK2 (GCLK0) GCLK2 (GCLK0)
Note: 1. Values in parentheses are for the M4(LV)-32/32 and M4(LV)-64/32.
This feature provides high flexibility for partitioning state machines and dual-phase clocks. It also allows latches to be driven with either polarity of latch enable, and in a master-slave configuration.
18
MACH 4 Family
MACH 4 TIMING MODEL
The primary focus of the MACH 4 timing model is to accurately represent the timing in a MACH 4 device, and at the same time, be easy to understand. This model accurately describes all combinatorial and registered paths through the device, making a distinction between internal feedback and external feedback. A signal uses internal feedback when it is fed back into the switch matrix or block without having to go through the output buffer. The input register specifications are also reported as internal feedback. When a signal is fed back into the switch matrix after having gone through the output buffer, it is using external feedback. The parameter, tBUF, is defined as the time it takes to go from feedback through the output buffer to the I/O pad. If a signal goes to the internal feedback rather than to the I/O pad, the parameter designator is followed by an "i". By adding tBUF to this internal parameter, the external parameter is derived. For example, tPD = tPDi + tBUF. A diagram representing the modularized MACH 4 timing model is shown in Figure 15. Refer to the Technical Note entitled MACH 4 Timing and High Speed Design for a more detailed discussion about the timing parameters.
(External Feedback)
(Internal Feedback)
COMB/DFF/TFF/ LATCH/SR*/JK* IN Central Switch Matrix
*emulated
tSLW tBUF
OUT
tPL INPUT REG/ INPUT LATCH tSIRS tHIRS tSIL tHIL tSIRZ tHIRZ tSILZ tHILZ BLK CLK tPDILi tICOSi tIGOSi tPDILZi Q
tSS(T) tSA(T) tH(S/A) tS(S/A)L tH(S/A)L tSRR
tPDi Q tPDLi tCO(S/A)i tGO(S/A)i tSRi
S/R
tEA tER
17466G-025
Figure 15. MACH 4 Timing Model
SPEEDLOCKING FOR GUARANTEED FIXED TIMING
The MACH 4 architecture allows allocation of up to 20 product terms to an individual macrocell with the assistance of an XOR gate without incurring additional timing delays. The design of the switch matrix and PAL blocks guarantee a fixed pin-to-pin delay that is independent of the logic required by the design. Other competitive CPLDs incur serious timing delays as product terms expand beyond their typical 4 or 5 product term limits. Speed and SpeedLocking combine to give designs easy access to the performance required in today's designs.
MACH 4 Family
19
IEEE 1149.1-COMPLIANT BOUNDARY SCAN TESTABILITY
All MACH 4 devices, except the M4(LV)-128N/64, have boundary scan cells and are compliant to the IEEE 1149.1 standard. This allows functional testing of the circuit board on which the device is mounted through a serial scan path that can access all critical logic nodes. Internal registers are linked internally, allowing test data to be shifted in and loaded directly onto test nodes, or test node data to be captured and shifted out for verification. In addition, these devices can be linked into a board-level serial scan path for more complete board-level testing.
IEEE 1149.1-COMPLIANT IN-SYSTEM PROGRAMMING
Programming devices in-system provides a number of significant benefits including: rapid prototyping, lower inventory levels, higher quality, and the ability to make in-field modifications. All MACH 4 devices provide In-System Programming (ISP) capability through their Boundary ScanTest Access Ports. This capability has been implemented in a manner that ensures that the port remains compliant to the IEEE 1149.1 standard. By using IEEE 1149.1 as the communication interface through which ISP is achieved, customers get the benefit of a standard, well-defined interface. MACH 4 devices can be programmed across the commercial temperature and voltage range. The PC-based LatticePRO software facilitates in-system programming of MACH 4 devices. LatticePRO takes the JEDEC file output produced by the design implementation software, along with information about the JTAG chain, and creates a set of vectors that are used to drive the JTAG chain. LatticePRO software can use these vectors to drive a JTAG chain via the parallel port of a PC. Alternatively, LatticePRO software can output files in formats understood by common automated test equipment. This equpment can then be used to program MACH 4 devices during the testing of a circuit board.
PCI COMPLIANT
MACH 4 devices in the -7/-10/-12 speed grades are compliant with the PCI Local Bus Specification version 2.1, published by the PCI Special Interest Group (SIG). The 5-V devices are fully PCI-compliant. The 3.3-V devices are mostly compliant but do not meet the PCI condition to clamp the inputs as they rise above VCC because of their 5-V input tolerant feature.
SAFE FOR MIXED SUPPLY VOLTAGE SYSTEM DESIGNS
Both the 3.3-V and 5-V VCC MACH 4 devices are safe for mixed supply voltage system designs. The 5-V devices will not overdrive 3.3-V devices above the output voltage of 3.3 V, while they accept inputs from other 3.3-V devices. The 3.3-V device will accept inputs up to 5.5 V. Both the 5-V and 3.3-V versions have the same high-speed performance and provide easy-to-use mixedvoltage design capability.
BUS-FRIENDLY INPUTS AND I/OS
All MACH 4 devices have inputs and I/Os which feature the Bus-Friendly circuitry incorporating two inverters in series which loop back to the input. This double inversion weakly holds the input at its last driven logic state. While it is good design practice to tie unused pins to a known state, the Bus-Friendly input structure pulls pins away from the input threshold voltage where noise can cause high-frequency switching. At power-up, the Bus-Friendly latches are reset to a logic level "1." For the circuit diagram, please refer to the document entitled MACH Endurance Characteristics on the Lattice/Vantis Data Book CD-ROM or Lattice web site.
20 MACH 4 Family
POWER MANAGEMENT
Each individual PAL block in MACH 4 devices features a programmable low-power mode, which results in power savings of up to 50%. The signal speed paths in the low-power PAL block will be slower than those in the non-low-power PAL block. This feature allows speed critical paths to run at maximum frequency while the rest of the signal paths operate in the low-power mode.
PROGRAMMABLE SLEW RATE
Each MACH 4 device I/O has an individually programmable output slew rate control bit. Each output can be individually configured for the higher speed transition (3 V/ns) or for the lower noise transition (1 V/ns). For high-speed designs with long, unterminated traces, the slow-slew rate will introduce fewer reflections, less noise, and keep ground bounce to a minimum. For designs with short traces or well terminated lines, the fast slew rate can be used to achieve the highest speed. The slew rate is adjusted independent of power.
POWER-UP RESET/SET
All flip-flops power up to a known state for predictable system initialization. If a macrocell is configured to SET on a signal from the control generator, then that macrocell will be SET during device power-up. If a macrocell is configured to RESET on a signal from the control generator or is not configured for set/reset, then that macrocell will RESET on power-up. To guarantee initialization values, the VCC rise must be monotonic, and the clock must be inactive until the reset delay time has elapsed.
SECURITY BIT
A programmable security bit is provided on the MACH 4 devices as a deterrent to unauthorized copying of the array configuration patterns. Once programmed, this bit defeats readback of the programmed pattern by a device programmer, securing proprietary designs from competitors. Programming and verification are also defeated by the security bit. The bit can only be reset by erasing the entire device.
MACH 4 Family
21
CLK0 CLK1 CLK2 CLK3
M4(LV)-64/32, M4(LV)-96/48, M4(LV)-128/64 A B 16 17
M4(LV)-192/96, M4(LV)-256/128 17 17
A
CLOCK GENERATOR 4 0
C0
M0 M0 M1 MACROCELL M1 O0 I/O CELL MACROCELL I/O0
C1
C2
M2 M2 M3 MACROCELL M3 O1 MACROCELL I/O CELL I/O1
C3
C4
M4 M4 M5 MACROCELL M5 O2 MACROCELL I/O CELL I/O2
C5
C6 CENTRAL SWITCH MATRIX LOGIC ALLOCATOR
M6 OUTPUT SWITCH MATRIX M6 M7 MACROCELL M7 MACROCELL O3 I/O CELL I/O3
C7
C8
M8 M8 M9 MACROCELL M9 MACROCELL
O4
C9
I/O CELL
I/O4
C10
M10 M10 M11 MACROCELL M11 O5 MACROCELL I/O CELL I/O5
C11
C12
M12 M12 M13 MACROCELL M13 O6 I/O CELL MACROCELL I/O6
C13
C14
M14 M14 M15 MACROCELL M15 MACROCELL O7 I/O CELL I/O7
C15 89 B
16 24 INPUT SWITCH MATRIX 16
Figure 16. PAL Block for MACH 4 with 2:1 Macrocell - I/O Cell Ratio
22
MACH 4 Family
CLK0/I0 16
CLK0/I1
CLOCK GENERATOR 2
0
M0 C0 M0 M1 C1 MACROCELL M1 MACROCELL O1 O0
I/O CELL I/O CELL
I/O0
I/O1
C2
M2 M3 OUTPUT SWITCH MATRIX M2 M3 MACROCELL MACROCELL O2 O3
I/O CELL I/O CELL
I/O2
I/O3
C3
C4
M4 M4 M5 MACROCELL M5 MACROCELL
O4
I/O CELL I/O CELL
I/O4
I/O5
C5
O5
CENTRAL SWITCH MATRIX
C6 LOGIC ALLOCATOR
M6 M6 M7 MACROCELL M7 MACROCELL O7 O6
I/O CELL I/O CELL
I/O6
I/O7
C7
C8
M8 M8 M9 MACROCELL M9 MACROCELL O8
I/O CELL I/O CELL
I/O8
I/O9
C9
O9
C10
M10 M11 OUTPUT SWITCH MATRIX M10 MACROCELL MACROCELL O10
I/O CELL I/O CELL
I/O10
I/O11
C11 M11
O11
C12
M12 M12 MACROCELL M13 MACROCELL
O12
I/O CELL I/O CELL
I/O12
I/O13
C13 M13
O13
C14
M14 M14 MACROCELL M15 MACROCELL O14
I/O CELL I/O CELL
I/O14
C15 M15 97 17 16 32 INPUT SWITCH MATRIX
I/O15
O15
16
Figure 17. PAL Block for M4(LV)-32/32
17466H-042
MACH 4 Family
23
BLOCK DIAGRAM - M4(LV)-32/32
Block A
I/O8-I/O15 I/O0-I/O7
8 I/O Cells Clock Generator 8 Output Switch Matrix 8 Macrocells OE 8 Input Switch Matrix 2 OE 8 4
8 I/O Cells 8 Output Switch Matrix 8 8 Macrocells 8 Input Switch Matrix 16 16 Input Switch Matrix 8 Macrocells 8 Clock Generator 4 8 4 8 8 8 Output Switch Matrix 8 I/O Cells 8 I/O24-I/O31
8 8
8 4
8
66 X 98 AND Logic Array and Logic Allocator 33
CLK0/I0, CLK1/I1
16
2 2 16 Input Switch Matrix
Central Switch Matrix
33 66 X 98 AND Logic Array and Logic Allocator OE OE
8 Macrocells 8 8 8 Output Switch Matrix 8 I/O Cells 8
2
I/O16-I/O23
Block B
17466H-019
24
MACH 4 Family
BLOCK DIAGRAM - M4(LV)-64/32
Block A
I/O0-I/O7
Block D
I/O24-I/O31
8 I/O Cells Clock Generator Clock Generator 4 8 4 8 Output Switch Matrix 16 Macrocells OE OE 16 Input Switch Matrix 66 X 90 AND Logic Array and Logic Allocator 2 4 8 4
8 I/O Cells 8 Output Switch Matrix 16 16 Macrocells 16 66 X 90 AND Logic Array and Logic Allocator Input Switch Matrix 24 24 Input Switch Matrix 16 16 8 4 Output Switch Matrix 8 I/O Cells 8 16
16 16
16
2
CLK0/I0, CLK1/I1
33
24
33
2 2 33
Central Switch Matrix
24 Input Switch Matrix 33 66 X 90 AND Logic Array and Logic Allocator OE 16 Macrocells 16 16 8 4 Output Switch Matrix 8 I/O Cells 8 16 Clock Generator 4
2 OE Clock Generator 4
66 X 90 AND Logic Array and Logic Allocator 16 Macrocells
2
I/O8-I/O15
I/O16-I/O23
Block B
Block C
17466H-020
MACH 4 Family
25
26
Block C
I/O16-I/O23 I/O8-I/O15 I/O0-I/O7
Block B
Block A
8 I/O Cells 4 8 16 16 16 Macrocells OE OE 16 Input Switch Matrix 66 X 90 AND Logic Array and Logic Allocator 4 24 66 X 90 AND Logic Array and Logic Allocator 16 Macrocells 4 16 16 4 16 16 16 4 Macrocells OE 16 Input Switch Matrix 66 X 90 AND Logic Array and Logic Allocator 4 24 33 16 Output Switch Matrix 8 8 Output Switch Matrix Output Switch Matrix Clock Generator Clock Generator 8 4 4 8 33 33 24 Input Switch Matrix 4 8 Clock Generator I/O Cells I/O Cells
BLOCK DIAGRAM - M4(LV)-96/48
8 8
4 4 33 24 33 24
I2, I3, I6, I7
Central Switch Matrix
33 24
CLK0/I0, CLK1/I1, CLK2/I4, CLK3/I5
MACH 4 Family
Input Switch Matrix Input Switch Matrix 4 OE 16 16 Macrocells 16 16 8 Output Switch Matrix 8 I/O Cells 8 4 16 8 4 4 16 16 Output Switch Matrix 8 I/O Cells 8 16 4 8 4 Macrocells 4 Clock Generator I/O24-I/O31 Clock Generator OE 66 X 90 AND Logic Array and Logic Allocator 4 66 X 90 AND Logic Array and Logic Allocator 4 OE Clock Generator I/O32-I/O39
4
Input Switch Matrix 66 X 90 AND Logic Array and Logic Allocator 16 Macrocells 16 16 Output Switch Matrix 8 I/O Cells 8 16
I/O40-I/O47
17466G-021
Block D
Block E
Block F
Block D I/O24-I/031 I/O16-I/O23 I/O8-I/O15 I/O0-I/O7
Block C
Block B
Block A
8 8 I/O Cells 4 8 4 16 Macrocells OE 16 Output Switch Matrix 8 I/O Cells 8 4 8 16 16 Macrocells OE OE 16 4 4 Input Switch Matrix Input Switch Matrix 66 X 90 AND Logic Array and Logic Allocator 24 33 24 33 66 X 90 AND Logic Array and Logic Allocator 16 Macrocells 4 16 16 16 4 16 Output Switch Matrix 8 Output Switch Matrix 4 Output Switch Matrix 16 16 16 Macrocells 16 Input Switch Matrix 4 8 8 I/O Cells I/O Cells
8 8
4
Input Switch Matrix
4
Clock Generator Clock Generator Clock Generator 16 16 66 X 90 AND Logic Array and Logic Allocator 33 24 33 24
Clock Generator
8
4
OE
66 X 90 AND Logic Array and Logic Allocator
I2, I5
4 33 24 33 24 33
Central Switch Matrix
24 33 24
CLK0/I0, CLK1/I1, CLK2/I3, CLK3/I4
BLOCK DIAGRAM - M4(LV)-128N/64 AND M4(LV)-128/64
MACH 4 Family
Input Switch Matrix Input Switch Matrix Input Switch Matrix 4 OE OE 66 X 90 AND Logic Array and Logic Allocator 4 16 Macrocells 16 16 Output Switch Matrix 8 8 I/O Cells 8 I/O Cells 8 4 16 8 Output Switch Matrix 16 4 16 16 4 8 4 66 X 90 AND Logic Array and Logic Allocator 16 Macrocells 16 16 Output Switch Matrix 8 I/O Cells 8 16 16 Macrocells Clock Generator Clock Generator I/O32-I/O39 Block E I/O40-I/O47 Block F I/O48-I/O55 Block G
4
2
Input Switch Matrix
4
66 X 90 AND Logic Array and Logic Allocator
4 OE
66 X 90 AND Logic Array and Logic Allocator 16 Macrocells 4 8 4
4
Clock Generator
Clock Generator
4
OE
16 16 Output Switch Matrix 8 I/O Cells 8 16
8
I/O56-I/O63 Block H
17466H-022
27
BLOCK DIAGRAM - M4(LV)-192/96
Block B I/O8-I/O15
Block A I/O0-I/O7
CLK0-CLK3
Block L I/O88-I/O95
Block K I/O80-I/O87
8
8
4
4 8 8
I/O Cells Clock Generator
8 4 8 4
I/O Cells
8
I/O Cells Clock Generator Clock Generator
4 8 4 4 8 4 8
I/O Cells Clock Generator
4 8 4 8
Output Switch Matrix
16 16 16
16
Output Switch Matrix
16
Output Switch Matrix
16 16
Output Switch Matrix
16 16
Macrocells
OE 16
16
Macrocells
OE OE 16
Macrocells
16
16 OE
Macrocells
16
16
Input Switch Matrix
Input Switch Matrix
Input Switch Matrix
68 X 90 AND Logic Array and Logic Allocator
34
4
68 X 90 AND Logic Array and Logic Allocator
34
4
4
68 X 90 AND Logic Array and Logic Allocator
34
4
68 X 90 AND Logic Array and Logic Allocator
34
24
24
24
24
Input Switch Matrix
Block C I/O16-I/O23 Block D I/O24-I/O31
8 8 8 8
I/O72-I/O79 Block J I/O64-I/O71 Block I
I/O Cells Clock Generator
8 4 8 4
I/O Cells
I/O Cells
I/O Cells Clock Generator
4 8 4 8
Central Switch Matrix
8
Clock Generator
Clock Generator
4 8 4
4 8 4
8
Output Switch Matrix
16 16 16
Output Switch Matrix
16 16 16
Output Switch Matrix
16 16
Output Switch Matrix
16 16
Macrocells
OE 16
Macrocells
OE 16
Macrocells
OE 16
16 OE
Macrocells
16
16
Input Switch Matrix
Input Switch Matrix
Input Switch Matrix
68 X 90 AND Logic Array and Logic Allocator
34
4
68 X 90 AND Logic Array and Logic Allocator
34
4
4
68 X 90 AND Logic Array and Logic Allocator
34
4
68 X 90 AND Logic Array and Logic Allocator
34
24
24
24
24
24
34
24
34
34
24
34
24
Input Switch Matrix
Input Switch Matrix
Input Switch Matrix
68 X 90 AND Logic Array and Logic Allocator
OE 16
4
68 X 90 AND Logic Array and Logic Allocator
OE 16
4
4 OE
68 X 90 AND Logic Array and Logic Allocator
16
4 OE
68 X 90 AND Logic Array and Logic Allocator
16
16
Macrocells Clock Generator
16 4 8 4
16
Macrocells
16
Macrocells Clock Generator Clock Generator
4 8 4 4 8 4 16
16
Macrocells Clock Generator
4 8 4 16
16
16
Output Switch Matrix
8
16
Output Switch Matrix
8
Output Switch Matrix
8
16
Output Switch Matrix
8
I/O Cells
8
I/O Cells
8
I/O Cells
8
I/O Cells
8
16
I/O32-I/O39 Block E
I/O40-I/O47 Block F
I0-I15
I/O48-I/O55 Block G
I/O56-I/O63 Block H
Input Switch Matrix
16
Input Switch Matrix
17466G-067
28
MACH 4 Family
BLOCK DIAGRAM - M4(LV)-256/128
Block B I/O8-I/O15 Block A I/O0-I/O7 CLK0-CLK3 Block P I/O120-I/O127 Block O I/O112-I/O119
8
8
4
4 8 8
I/O Cells Clock Generator
8 4 8 4
I/O Cells
8
I/O Cells Clock Generator Clock Generator
4 8 4 4 8 4 8
I/O Cells Clock Generator
4 8 4 8
Output Switch Matrix
16 16 16
16
Output Switch Matrix
16
Output Switch Matrix
16 16
Output Switch Matrix
16 16
Macrocells
OE 16
16
Macrocells
OE OE 16
Macrocells
16
16 OE
Macrocells
16
16
Input Switch Matrix
Input Switch Matrix
Input Switch Matrix
68 X 90 AND Logic Array and Logic Allocator
34
4
68 X 90 AND Logic Array and Logic Allocator
34
4
4
68 X 90 AND Logic Array and Logic Allocator
34
4
68 X 90 AND Logic Array and Logic Allocator
34
24
24
24
24
24
34
24
34
34
24
34
24
Input Switch Matrix
Input Switch Matrix
Input Switch Matrix
68 X 90 AND Logic Array and Logic Allocator
OE 16
4
68 X 90 AND Logic Array and Logic Allocator
OE 16
4
4 OE
68 X 90 AND Logic Array and Logic Allocator
16
4 OE
68 X 90 AND Logic Array and Logic Allocator
16
16
Macrocells Clock Generator
16 4 8 4
16
Macrocells
16
Macrocells Clock Generator Clock Generator
4 8 4 4 8 4 16
16
Macrocells Clock Generator
4 8 4 16
16
16
Output Switch Matrix
8
16
Output Switch Matrix
8
Output Switch Matrix
8
16
Output Switch Matrix
8
I/O Cells
8
I/O Cells
I/O Cells
I/O Cells
8
8
Central Switch Matrix
Block C I/O16-I/O23 Block D I/O24-I/O31 Block E I/O32-I/O39 Block F I/O40-I/O47
8 8
8
Input Switch Matrix
16
Input Switch Matrix
I/O104-I/O111 Block N I/O96-I/O103 Block M I/O88-I/O95 Block L I/O80-I/O87 Block K
8
8
I/O Cells Clock Generator
8 4 8 4
I/O Cells Clock Generator
8
I/O Cells Clock Generator
4 8 4 4 8 4 8
I/O Cells Clock Generator
4 8 4 8
Output Switch Matrix
16 16 16
Output Switch Matrix
16 16 16
Output Switch Matrix
16 16
Output Switch Matrix
16 16
Macrocells
OE 16
Macrocells
OE OE 16
Macrocells
16
16 OE
Macrocells
16
16
Input Switch Matrix
Input Switch Matrix
Input Switch Matrix
68 X 90 AND Logic Array and Logic Allocator
34
4
68 X 90 AND Logic Array and Logic Allocator
34
4
4
68 X 90 AND Logic Array and Logic Allocator
34
4
68 X 90 AND Logic Array and Logic Allocator
34
24
24
24
24
24
34
24
34
34
24
34
24
Input Switch Matrix
Input Switch Matrix
Input Switch Matrix
68 X 90 AND Logic Array and Logic Allocator
OE 16
4
68 X 90 AND Logic Array and Logic Allocator
OE 16
4
4 OE
68 X 90 AND Logic Array and Logic Allocator
16
4 OE
68 X 90 AND Logic Array and Logic Allocator
16
16
Macrocells Clock Generator
16 4 8 4
16
Macrocells
16
Macrocells Clock Generator Clock Generator
4 8 4 4 8 4 16
16
Macrocells Clock Generator
4 8 4 16
16
16
Output Switch Matrix
8
16
Output Switch Matrix
8
Output Switch Matrix
8
16
Output Switch Matrix
8
I/O Cells
8
I/O Cells
8
I/O Cells
8
I/O Cells
8
14
Input Switch Matrix
16
Input Switch Matrix
I/O48-I/O55 Block G
I/O56-I/O63 Block H
I0-I13
I/O64-I/O71 Block I
I/O72-I/O79 Block J
17466G-024
MACH 4 Family
29
ABSOLUTE MAXIMUM RATINGS
M4
Storage Temperature . . . . . . . . . . . . . .-65C to +150C Ambient Temperature with Power Applied . . . . . . . . . . . . . . -55C to +100C Device Junction Temperature . . . . . . . . . . . . . +130C Supply Voltage with Respect to Ground . . . . . . . . . . . -0.5 V to +7.0 V DC Input Voltage . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Static Discharge Voltage . . . . . . . . . . . . . . . . . 2000 V Latchup Current (TA = -40C to +85C). . . . . . . 200 mA
Str esses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability.
OPERATING RANGES
Commercial (C) Devices
Ambient Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . . 0C to +70C Supply Voltage (VCC) with Respect to Ground . . . . . . . . . +4.75 V to +5.25 V
Industrial (I) Devices
Ambient Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . -40C to +85C Supply Voltage (VCC) with Respect to Ground . . . . . . . . . . +4.50 V to +5.5 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
5-V DC CHARACTERISTICS OVER OPERATING RANGES
Parameter Symbol VOH VOL VIH VIL IIH IIL IOZH IOZL ISC Parameter Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input HIGH Leakage Current Input LOW Leakage Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current LOW Output Short-Circuit Current Test Conditions IOH = -3.2 mA, VCC = Min, VIN = VIH or VIL IOH = 0 mA, VCC = Max, VIN = VIH or VIL IOL = 24 mA, VCC = Min, VIN = VIH or VIL (Note 1) Guaranteed Input Logical HIGH Voltage for all Inputs (Note 2) Guaranteed Input Logical LOW Voltage for all Inputs (Note 2) VIN = 5.25 V, VCC = Max (Note 3) VIN = 0 V, VCC = Max (Note 3) VOUT = 5.25 V, VCC = Max, VIN = VIH or VIL (Note 3) VOUT = 0 V, VCC = Max , VIN = VIH or VIL (Note 3) VOUT = 0.5 V, VCC = Max (Note 4) -30 2.0 0.8 10 -10 10 -10 -160 Min 2.4 3.3 0.5 Typ Max Unit V V V V V A A A A mA
Notes: 1. Total IOL for one PAL block should not exceed 64 mA. 2. These are absolute values with respect to device ground, and all overshoots due to system or tester noise are included. 3. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 4. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
MACH 4 Family
30
ABSOLUTE MAXIMUM RATINGS
M4LV
Storage Temperature . . . . . . . . . . . . . .-65C to +150C Ambient Temperature with Power Applied . . . . . . . . . . . . . . -55C to +100C Device Junction Temperature . . . . . . . . . . . . . +130C Supply Voltage with Respect to Ground . . . . . . . . . . . -0.5 V to +4.5 V DC Input Voltage . . . . . . . . . . . . . . . . . -0.5 V to 6.0 V Static Discharge Voltage . . . . . . . . . . . . . . . . . 2000 V Latchup Current (TA = -40C to +85C). . . . . . . 200 mA
Str esses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability.
OPERATING RANGES
Commercial (C) Devices
Ambient Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . . 0C to +70C Supply Voltage (VCC) with Respect to Ground . . . . . . . . . . . +3.0 V to +3.6 V
Industrial (I) Devices
Ambient Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . -40C to +85C Supply Voltage (VCC) with Respect to Ground . . . . . . . . . . . +3.0 V to +3.6 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
3.3-V DC CHARACTERISTICS OVER OPERATING RANGES
Parameter Symbol VOH Parameter Description Output HIGH Voltage Test Conditions VCC = Min VIN = VIH or VIL VCC = Min VIN = VIH or VIL (Note 1) IOH = -100 A IOH = -3.2 mA IOL = 100 A IOL = 24 mA 2.0 -0.3 Min VCC - 0.2 2.4 0.2 0.5 5.5 0.8 5 -5 5 -5 -15 -160 Typ Max Unit V V V V V V A A A A mA
VOL VIH VIL IIH IIL IOZH IOZL ISC
Output LOW Voltage
Input HIGH Voltage Input LOW Voltage Input HIGH Leakage Current Input LOW Leakage Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current LOW Output Short-Circuit Current
Guaranteed Input Logical HIGH Voltage for all Inputs Guaranteed Input Logical LOW Voltage for all Inputs VIN = 3.6 V, VCC = Max (Note 2) VIN = 0 V, VCC = Max (Note 2) VOUT = 3.6 V, VCC = Max VIN = VIH or VIL (Note 2) VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 2) VOUT = 0.5 V, VCC = Max (Note 3)
Notes: 1. Total IOL for one PAL block should not exceed 64 mA. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.
MACH 4 Family
31
MACH 4 TIMING PARAMETERS OVER OPERATING RANGES1
-7 Min Combinatorial Delay: tPDi tPD tSS tSST tSA tSAT tHS tHA tCOSi tCOS tCOAi tCOA tSSL tSAL tHSL tHAL tPDLi tPDL tGOSi tGOS tGOAi tGOA tSIRS tHIRS tICOSi tSIL tHIL tIGOSi tPDILi tSIRZ tHIRZ Internal combinatorial propagation delay Combinatorial propagation delay Synchronous clock setup time, D-type register Synchronous clock setup time, T-type register Asynchronous clock setup time, D-type register Asynchronous clock setup time, T-type register Synchronous clock hold time Asynchronous clock hold time Synchronous clock to internal output Synchronous clock to output Asynchronous clock to internal output Asynchronous clock to output Synchronous Latch setup time Asynchronous Latch setup time Synchronous Latch hold time Asynchronous Latch hold time Transparent latch to internal output Propagation delay through transparent latch to output Synchronous Gate to internal output Synchronous Gate to output Asynchronous Gate to internal output Asynchronous Gate to output Input register setup time Input register hold time Input register clock to internal feedback Input latch setup time Input latch hold time Input latch gate to internal feedback Transparent input latch to internal feedback Input register setup time - ZHT Input register hold time - ZHT 6.0 0.0 2.0 3.0 4.0 2.0 6.0 0.0 2.0 3.0 3.5 2.0 3.0 4.0 2.0 6.0 0.0 6.0 4.0 0.0 4.0 8.0 10.0 4.0 6.0 9.0 11.0 2.0 3.0 4.5 2.0 3.0 4.0 2.0 6.0 0.0 5.5 6.5 3.5 4.5 0.0 3.5 3.5 5.5 7.5 9.5 7.0 4.0 0.0 4.0 10.0 12.0 5.5 7.5 11.0 13.0 2.0 3.0 6.0 2.0 4.0 5.0 2.0 6.0 0.0 5.5 7.5 6.0 7.0 4.0 5.0 0.0 4.0 4.5 6.5 10.0 12.0 8.0 5.0 0.0 5.0 12.0 14.0 8.0 10.0 14.0 16.0 2.0 4.0 6.0 2.0 4.0 5.0 2.0 6.0 0.0 8.0 10.0 7.0 8.0 5.0 6.0 0.0 5.0 6.0 8.0 12.0 14.0 10.0 8.0 0.0 8.0 15.0 17.0 9.0 11.0 17.0 19.0 2.0 4.0 6.0 2.0 4.0 6.0 2.0 10.0 12.0 10.0 11.0 8.0 9.0 0.0 8.0 8.0 10.0 16.0 18.0 10.0 8.0 0.0 8.0 15.0 17.0 9.0 11.0 17.0 19.0 2.0 4.0 6.0 12.0 14.0 10.0 11.0 8.0 9.0 0.0 8.0 8.0 10.0 16.0 18.0 12.0 10.0 0.0 10.0 18.0 20.0 10.0 12.0 20.0 22.0 13.0 15.0 12.0 13.0 10.0 11.0 0.0 10.0 10.0 12.0 18.0 20.0 16.0 18.0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Max -10 Min -12 -14 -15 -18 Unit Max Min Max Min Max Min Max Min Max
Registered Delays:
Latched Delays:
Input Register Delays:
Input Latch Delays:
Input Register Delays with ZHT Option:
32
MACH 4 Family
MACH 4 TIMING PARAMETERS OVER OPERATING RANGES1 (CONTINUED)
-7 Min Input Latch Delays with ZHT Option: tSILZ tHILZ Input latch setup time - ZHT Input latch hold time - ZHT 6.0 0.0 6.0 2.0 2.5 9.5 9.5 2.5 10.0 12.0 8.0 10.0 3.0 3.0 4.0 4.0 5.0 4.0 4.5 4.5 5.0 8.0 10.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 6.0 0.0 6.0 2.0 2.5 10.0 10.0 2.5 12.0 14.0 10.0 12.0 6.0 6.0 8.0 8.0 6.0 6.0 6.0 6.0 6.0 6.0 0.0 6.0 2.0 2.5 12.0 12.0 2.5 14.0 16.0 15.0 15.0 6.0 6.0 9.0 9.0 6.0 9.0 6.0 6.0 6.0 6.0 0.0 6.0 2.0 2.5 15.0 15.0 2.5 18.0 20.0 15.0 15.0 6.0 6.0 9.0 9.0 6.0 9.0 6.0 6.0 6.0 6.0 0.0 6.0 2.0 2.5 15.0 15.0 2.5 18.0 20.0 17.0 17.0 7.0 7.0 10.0 10.0 7.0 11.0 7.0 7.0 7.0 6.0 0.0 6.0 2.0 2.5 17.0 17.0 2.5 20.0 22.0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Max -10 Min -12 -14 -15 -18 Unit Max Min Max Min Max Min Max Min Max
tPDILZi Transparent input latch to internal feedback - ZHT Output Delays: tBUF tSLW tEA tER tPL tSRi tSR tSRR tSRW tWLS tWHS tWLA tWHA tGWS tGWA tWIRL tWIRH tWIL Output buffer delay Slow slew rate delay adder Output enable time Output disable time Power-down mode delay adder Asynchronous reset or preset to internal register output Asynchronous reset or preset to register output Asynchronous reset and preset register recovery time Asynchronous reset or preset width Global clock width low Global clock width high Product term clock width low Product term clock width high Global gate width low (for low transparent) or high (for high transparent) Product term gate width low (for low transparent) or high (for high transparent) Input register clock width low Input register clock width high Input latch gate width
Power Delay: Reset and Preset Delays:
Clock/LE Width:
MACH 4 Family
33
MACH 4 TIMING PARAMETERS OVER OPERATING RANGES1 (CONTINUED)
-7 Min Frequency: External feedback, D-type, Min of 1/(tWLS + tWHS) or 1/(tSS + tCOS) External feedback, T-type, Min of 1/(tWLS + tWHS) or 1/(tSST + tCOS) fMAXS Internal feedback (fCNT), D-type, Min of 1/(tWLS + tWHS) or 1/(tSS + tCOSi) Internal feedback (fCNT), T-type, Min of 1/(tWLS + tWHS) or 1/(tSST + tCOSi) 90.9 83.3 111.1 100.0 80.0 74.1 95.2 87.0 100.0 62.5 58.8 71.4 66.7 100.0 100.0 66.7 62.5 76.9 71.4 83.3 52.6 50.0 58.8 55.6 62.5 83.3 50.0 47.6 55.6 52.6 83.3 38.5 37.0 41.7 40.0 55.6 83.3 50.0 47.6 55.6 52.6 83.3 38.5 37.0 41.7 40.0 55.6 83.3 41.7 40.0 45.5 43.5 71.4 33.3 32.3 35.7 34.5 50.0 71.4 MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz Max -10 Min -12 -14 -15 -18 Unit Max Min Max Min Max Min Max Min Max
No feedback2, Min of 1/(tWLS + tWHS), 1/(tSS + tHS) or 153.8 1/(tSST + tHS) External feedback, D-type, Min of 1/(tWLA + tWHA) or 1/(tSA + tCOA) External feedback, T-type, Min of 1/(tWLA + tWHA) or 1/(tSAT + tCOA) fMAXA Internal feedback (fCNTA), D-type, Min of 1/(tWLA + tWHA) or 1/(tSA + tCOAi) Internal feedback (fCNTA), T-type, Min of 1/(tWLA + tWHA) or 1/(tSAT + tCOAi) No feedback2, Min of 1/(tWLA + tWHA), 1/(tSA + tHA) or 1/(tSAT + tHA) fMAXI Maximum input register frequency, Min of 1/(tWIRH + tWIRL) or 1/(tSIRS + tHIRS) 76.9 71.4 90.9 83.3 125.0 111.0
Notes: 1. See "MACH Switching Test Circuit" document on the Literature Download page of the Lattice web site. 2. This parameter does not apply to flip-flops in the emulated mode since the feedback path is required for emulation.
CAPACITANCE 1
Parameter Symbol CIN CI/O Parameter Description Input capacitance Output capacitance VIN=2.0 V VOUT=2.0V Test Conditions 3.3 V or 5 V, 25C, 1 MHz 3.3 V or 5 V, 25C, 1 MHz Typ 6 8 Unit pF pF
Note: 1. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where this parameter may be affected.
34
MACH 4 Family
ICC vs. FREQUENCY
These curves represent the typical power consumption for a particular device at system frequency. The selected "typical" pattern is a 16-bit up-down counter. This pattern fills the device and exercises every macrocell. Maximum frequency shown uses internal feedback and a D-type register. Power/Speed are optimized to obtain the highest counter frequency and the lowest power. The highest frequency (LSBs) is placed in common PAL blocks, which are set to high power. The lowest frequency signals (MSBs) are placed in a common PAL block and set to lowest power.
350 300 250 ICC (mA) 200 M4(LV)-128/64 150 M4(LV)-96/48 100 50 0 100 110 120 130 10 20 30 40 50 60 70 80 90 0 M4(LV)-64/32 M4(LV)-32/32 M4(LV)-192/96 VCC = 5 V or 3.3 V, TA = 25 C M4(LV)-256/128
Frequency (MHz)
17466G-066
Figure 18. MACH 4 ICC Curves at High Speed Mode
350 300 250 200 150 100 50 0 10 20 30 40 50 60 70 80 90 100 110 120 0 M4(LV)-256/128 M4(LV)-192/96 VCC = 5 V or 3.3 V, TA = 25 C
ICC (mA)
M4(LV)-128/64 M4(LV)-96/48 M4(LV)-64/32 M4(LV)-32/32
Frequency (MHz)
17466G-065
Figure 19. MACH 4 ICC Curves at Low Power Mode
MACH 4 Family
35
44-PIN PLCC CONNECTION DIAGRAM (M4(LV)-32/32 AND M4(LV)-64/32)
Top View
44-Pin PLCC
A3 A4 A5 A6 A7 B7 B6 I/O30 D6 B5 I/O29 D5 B4 I/O28 D4
M4(LV)-64/32
M4(LV)-64/32
6 A2 A1 A0 A2 A1 A0 I/O5 I/O6 I/O7 TDI M4(LV)-32/32 CLK0/I0 GND TCK A8 A9 A10 A11 B0 B1 I/O8 I/O9 7 8 9 10 11 12 13 14 15 16 17
5
4
3
2
1 44 43 42 41 40 39 38 37 I/O27 I/O26 I/O25 I/O24 TDO GND CLK1/I1 TMS I/O23 I/O22 I/O21 C0 C1 C2 B8 B9 B10 M4(LV)-32/32 D3 D2 D1 D0 B3 B2 B1 B0
C
7
I/O31 D7
I/O4 A3
I/O3 A4
I/O2 A5
I/O1 A6
I/O0 A7
GND
VCC
36 35 34 33 32 31 30 29
I/O Cell (0-7) PAL Block (A-D)
B2 I/O10 B3 I/O11
18 19 20 21 22 23 24 25 26 27 28
VCC
B4 I/O12
B5 I/O13
B6 I/O14
B7 I/O15
GND
C7 I/O16
C6 I/O17
C5 I/O18
C4 I/O19
M4(LV)-64/32
C3 I/O20 B11
M4(LV)-64/32
A12
A13
A14
A15
B15
B14
B13
B12
17466G-026
PIN DESIGNATIONS
CLK/I = Clock or Input GND = Ground I/O VCC TDI TCK TMS = Input/Output = Supply Voltage = Test Data In = Test Clock = Test Mode Select
TDO = Test Data Out
36
MACH 4 Family
44-PIN TQFP CONNECTION DIAGRAM (M4(LV)-32/32 AND M4(LV)-64/32)
Top View
44-Pin TQFP
A3 A4 A5 A6 A7 B7 B6 B5 B4 D7 D6 D5 D4
A2 A1 A0 M4(LV)-32/32
A8 A9 A10 A11
I/O5 I/O6 I/O7 TDI CLK0/I0 GND TCK I/O8 B0 I/O9 B1 B2 I/O10 B3 I/O11 A2 A1 A0
1 2 3 4 5 6 7 8 9 10 11
44 43 42 41 40 39 38 37 36 35 34
I/O4 I/O3 I/O2 I/O1 I/O0 GND VCC I/O31 I/O30 I/O29 I/O28
M4(LV)-64/32
A3 A4 A5 A6 A7
M4(LV)-64/32
C
7
I/O Cell (0-7) PAL Block (A-D)
33 32 31 30 29 28 27 26 25 24 23
I/O27 D3 I/O26 D2 I/O25 D1 I/O24 D0 TDO GND CLK1/I1 TMS I/O23 C0 I/O22 C1 I/O21 C2
B3 B2 B1 B0 M4(LV)-32/32
B8 B9 B10
M4(LV)-64/32
I/O12 I/O13 I/O14 I/O15 VCC GND I/O16 I/O17 I/O18 I/O19 I/O20
12 13 14 15 16 17 18 19 20 21 22
M4(LV)-64/32
B4 B5 B6 B7
A12 A13 A14 A15
PIN DESIGNATIONS
CLK/I = Clock or Input GND = Ground I/O VCC TDI TCK TMS = Input/Output = Supply Voltage = Test Data In = Test Clock = Test Mode Select
TDO = Test Data Out
MACH 4 Family
B15 B14 B13 B12 B11
C7 C6 C5 C4 C3
37
48-PIN TQFP CONNECTION DIAGRAM (M4(LV)-32/32 AND M4(LV)-64/32)
Top View
48-Pin TQFP
A3 A4 A5 A6 A7
A2 A1 A0
M4(LV)-32/32
A8 A9 A10 A11
I/O5 I/O6 I/O7 TDI CLK0/I0 NC GND TCK B0 I/O8 B1 I/O9 B2 I/O10 B3 I/O11 A2 A1 A0
1 2 3 4 5 6 7 8 9 10 11 12
48 47 46 45 44 43 42 41 40 39 38 37
I/O4 I/O3 I/O2 I/O1 I/O0 GND NC VCC I/O31 I/O30 I/O29 I/O28
M4(LV)-64/32
D7 D6 D5 D4
A3 A4 A5 A6 A7
B7 B6 B5 B4
M4(LV)-64/32
C
7
I/O Cell (0-7) PAL Block (A-D)
36 35 34 33 32 31 30 29 28 27 26 25
I/O27 D3 I/O26 D2 I/O25 D1 I/O24 D0 TDO GND NC CLK1/I1 TMS I/O23 C0 I/O22 C1 I/O21 C2
B3 B2 B1 B0 M4(LV)-32/32
B8 B9 B10
M4(LV)-64/32
I/O12 I/O13 I/O14 I/O15 VCC NC GND I/O16 I/O17 I/O18 I/O19 I/O20
13 14 15 16 17 18 19 20 21 22 23 24
M4(LV)-64/32
A12 A13 A14 A15
B15 B14 B13 B12 B11
C7 C6 C5 C4 C3
B4 B5 B6 B7
17466G-028
PIN DESIGNATIONS
CLK/I = Clock or Input GND = Ground I/O VCC NC TDI TCK TMS = Input/Output = Supply Voltage = No Connect = Test Data In = Test Clock = Test Mode Select
TDO = Test Data Out
38
MACH 4 Family
100-PIN TQFP CONNECTION DIAGRAM (M4(LV)-96/48)
Top View
100-Pin TQFP
A2 A3 A4 A5 A6 A7 F7 F6 F5 F4 F3 F2
NC TDI NC NC A1 I/O6 A0 I/O7 B0 I/O8 B1 I/O9 B2 I/O10 B3 I/O11 I0/CLK0 VCC GND I1/CLK1 B4 I/O12 B5 I/O13 B6 I/O14 B7 I/O15 C0 I/O16 C1 I/O17 NC NC TMS TCK NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
GND NC NC I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 I7 VCC GND NC NC I6 NC I/O47 I/O46 I/O45 I/O44 I/O43 I/O42 NC NC GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
C
7
I/O Cell (0-7) PAL Block (A-F)
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
NC TDO NC NC NC I/O41 I/O40 I/O39 I/O38 I/O37 I/O36 I5/CLK3 GND VCC I4/CLK2 I/O35 I/O34 I/O33 I/O32 I/O31 I/O30 NC NC NC NC
F1 F0 E0 E1 E2 E3
E4 E5 E6 E7 D0 D1
GND NC NC I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 NC I2 NC NC GND VCC I3 I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 NC NC GND
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
C2 C3 C4 C5 C6 C7
PIN DESIGNATIONS
CLK/I = Clock or Input GND = Ground I I/O VCC NC TDI TCK TMS = Input = Input/Output = Supply Voltage = No Connect = Test Data In = Test Clock = Test Mode Select
TDO = Test Data Out MACH 4 Family 39
D7 D6 D5 D4 D3 D2
17466G-029
84-PIN PLCC CONNECTION DIAGRAM (M4(LV)-128N/64)
Top View
84-Pin PLCC A7 A6 A5 A4 A3 A2 A1 A0 H0 H1 H2 H3 H4 H5 H6 H7 GND I/O55 G7 I/O54 G6 I/O53 G5 I/O52 G4 I/O51 G3 I/O50 G2 I/O49 G1 I/O48 G0 CLK3/I4 GND VCC CLK2/I3 I/O47 F0 I/O46 F1 I/O45 F2 I/O44 F3 I/O43 F4 I/O42 F5 I/O41 F6 I/O40 F7 E0 E1 E2 E3 E4 E5 E6 E7
B7 B6 B5 B4 B3 B2 B1 B0
I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 CLK0/I0 VCC GND CLK1/I1 C0 I/O16 I/O17 C1 C2 I/O18 C3 I/O19 C4 I/O20 C5 I/O21 C6 I/O22 C7 I/O23 GND
11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 12 74 13 73 72 14 71 15 70 16 17 69 68 18 67 19 C 7 66 20 21 65 64 22 I/O Cell (0-7) 63 23 62 24 PAL Block (A-H) 61 25 60 26 59 27 58 28 57 29 56 30 55 31 54 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 I2 VCC GND VCC I/O32 I/O33 I/O34 I/O35 I/O36 I/O37 I/O38 I/O39 GND D7 D6 D5 D4 D3 D2 D1 D0
GND I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 VCC GND VCC I5 I/O63 I/O62 I/O61 I/O60 I/O59 I/O58 I/O57 I/O56
17466G-030
Note: Pin-compatible with the MACH131, MACH231, MACH435.
PIN DESIGNATIONS
CLK/I = Clock or Input GND = Ground I I/O VCC = Input = Input/Output = Supply Voltage
40
MACH 4 Family
100-PIN PQFP CONNECTION DIAGRAM (M4(LV)-128/64)
Top View
100-Pin PQFP
A7 A6 A5 A4 A3 A2 A1 A0 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 VCC GND GND VCC I/O63 I/O62 I/O61 I/O60 I/O59 I/O58 I/O57 I/O56
(10) 100 (9) 99 (8) 98 (7) 97 (6) 96 (5) 95 (4) 94 (3) 93
I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 VCC GND GND VCC I/O32 I/O33 I/O34 I/O35 I/O36 I/O37 I/O38 I/O39
31 (33) 32 (34) 33 (35) 34 (36) 35 (37) 36 (38) 37 (39) 38 (40) 39 40 41 42 43 (45) 44 (46) 45 (47) 46 (48) 47 (49) 48 (50) 49 (51) 50 (52)
GND GND TDI I5 B7 I/O8 B6 I/O9 B5 I/O10 B4 I/O11 B3 I/O12 B2 I/O13 B1 I/O14 B0 I/O15 IO/CLK0 VCC VCC GND GND I1/CLK1 C0 I/O16 C1 I/O17 C2 I/O18 C3 I/O19 C4 I/O20 C5 I/O21 C6 I/O22 C7 I/O23 TMS TCK GND GND
1 2 3 4 (83) 5 (12) 6 (13) 7 (14) 8 (15) 9 (16) 10 (17) 11 (18) 12 (19) 13 (20) 14 15 16 17 18 (23) 19 (24) 20 (25) 21 (26) 22 (27) 23 (28) 24 (29) 25 (30) 26 (31) 27 28 29 30
(82) (81) (80) (79) (78) (77) (76) (75)
92 91 90 89 88 87 86 85 84 83 82 81
H0 H1 H2 H3 H4 H5 H6 H7
C
7
I/O Cell (0-7) PAL Block (A-H)
80 79 78 77 (73) 76 (72) 75 (71) 74 (70) 73 (69) 72 (68) 71 (67) 70 (66) 69 (65) 68 67 66 65 64 (62) 63 (61) 62 (60) 61 (59) 60 (58) 59 (57) 58 (56) 57 (55) 56 (54) 55 (41) 54 53 52 51
GND GND TD0 TRST G7 I/O55 G6 I/O54 G5 I/O53 G4 I/O52 G3 I/O51 G2 I/O50 G1 I/O49 G0 I/O48 I4/CLK3 GND GND VCC VCC I3/CLK2 F0 I/O47 F1 I/O46 F2 I/O45 F3 I/O44 F4 I/O43 F5 I/O42 F6 I/O41 F7 I/O40 I2 ENABLE GND GND
Note: The numbers in parentheses reflect compatible pin numbers for 84-pin PLCC.
PIN DESIGNATIONS
I/CLK = Input or Clock GND = Ground I I/O VCC TDI TCK TMS = Input = Input/Output = Supply Voltage = Test Data In = Test Clock = Test Mode Select
TDO = Test Data Out TRST = Test Reset
ENABLE = Program MACH 4 Family 41
D7 D6 D5 D4 D3 D2 D1 D0
E0 E1 E2 E3 E4 E5 E6 E7
17466G-031
100-PIN TQFP CONNECTION DIAGRAM (M4(LV)-128/64)
Top View
100-Pin TQFP
GND GND I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 VCC GND GND VCC I5 I/O63 I/O62 I/O61 I/O60 I/O59 I/O58 I/O57 I/O56 GND GND H0 H1 H2 H3 H4 H5 H6 H7 A7 A6 A5 A4 A3 A2 A1 A0
GND TDI B7 I/O8 B6 I/O9 B5 I/O10 B4 I/O11 B3 I/O12 B2 I/O13 B1 I/O14 B0 I/O15 I0/CLK0 VCC GND I1/CLK1 C0 I/O16 C1 I/O17 C2 I/O18 C3 I/O19 C4 I/O20 C5 I/O21 C6 I/O22 C7 I/O23 TMS TCK GND
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
C
7
I/O Cell (0-7) PAL Block (A-H)
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
GND TDO TRST I/O55 I/O54 I/O53 I/O52 I/O51 I/O50 I/O49 I/O48 I4/CLK3 GND VCC I3/CLK2 I/O47 I/O46 I/O45 I/O44 I/O43 I/O42 I/O41 I/O40 ENABLE GND
G7 G6 G5 G4 G3 G2 G1 G0
F0 F1 F2 F3 F4 F5 F6 F7
GND GND I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 I2 VCC GND GND VCC I/O32 I/O33 I/O34 I/O35 I/O36 I/O37 I/O38 I/O39 GND GND
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
D7 D6 D5 D4 D3 D2 D1 D0
PIN DESIGNATIONS
CLK/I = Clock or Input GND = Ground I I/O VCC TDI TCK TMS = Input = Input/Output = Supply Voltage = Test Data In = Test Clock = Test Mode Select
TDO = Test Data Out TRST = Test Reset
ENABLE = Program
42
MACH 4 Family
E0 E1 E2 E3 E4 E5 E6 E7
17466G-032
144-PIN TQFP CONNECTION DIAGRAM (M4(LV)-192/96)
Top View
144-Pin TQFP
B7 B6 B5 B4 B3 B2 B1 B0 A7 A6 A5 A4 A3 A2 A1 A0 L0 L1 L2 L3 L4 L5 L6 L7
D7 D6 D5 D4 D3 D2 D1 D0
C7 C6 C5 C4 C3 C2 C1 C0
E7 E6 E5 E4 E3 E2 E1 E0
GND TDI I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I2 I3 VCC GND I4 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 GND VCC I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 TMS TCK GND
144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109
I/O95 I/O94 I/O93 I/O92 I/O91 I/O90 I/O89 I/O88 GND VCC I/O87 I/O86 I/O85 I/O84 I/O83 I/O82 I/O81 I/O80 I1 I0 CLK0 GND VCC CLK3 I15 I14 I13 I/O79 I/O78 I/O77 I/O76 I/O75 I/O74 I/O73 I/O72 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
C
7
I/O Cell (0-7) PAL Block (A-L)
108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
GND TDO NC I/O71 I/O70 I/O69 I/O68 I/O67 I/O66 I/O65 I/O64 I12 VCC GND I11 I10 I/O63 I/O62 I/O61 I/O60 I/O59 I/O58 I/O57 I/O56 GND VCC I/O55 I/O54 I/O53 I/O52 I/O51 I/O50 I/O49 I/O48 NC GND
K0 K1 K2 K3 K4 K5 K6 K7
J0 J1 J2 J3 J4 J5 J6 J7 I0 I1 I2 I3 I4 I5 I6 I7
G0 G1 G2 G3 G4 G5 G6 G7
H0 H1 H2 H3 H4 H5 H6 H7
F7 F6 F5 F4 F3 F2 F1 F0
GND I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 I5 I6 I7 CLK1 GND VCC CLK2 I8 I9 I/O32 I/O33 I/O34 I/O35 I/O36 I/O37 I/O38 I/O39 VCC GND I/O40 I/O41 I/O42 I/O43 I/O44 I/O45 I/O46 I/O47
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
17466G-033
PIN DESIGNATIONS
CLK = Clock GND = Ground I I/O VCC TDI TCK TMS = Input = Input/Output = Supply Voltage = Test Data In = Test Clock = Test Mode Select
17466G-044
TDO = Test Data Out
MACH 4 Family
43
208-PIN PQFP CONNECTION DIAGRAM (M4(LV)-256/128)
Top View
208-Pin PQFP
C7 C6 C5 C4 C3 C2 C1 C0
D7 D6 D5 D4 D3 D2 D1 D0
E0 E1 E2 E3 E4 E5 E6 E7
F0 F1 F2 F3 F4 F5 F6 F7
GND TDI I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 VCC GND I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 I2 I3 GND VCC VCC GND GND VCC VCC GND I4 I/O32 I/O33 I/O34 I/O35 I/O36 I/O37 I/O38 I/O39 GND VCC I/O40 I/O41 I/O42 I/O43 I/O44 I/O45 I/O46 I/O47 TMS TCK GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157
156 155 RECOMMEND TO TIE TO VCC 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 I/O Cell (0-7) 124 123 PAL Block (A-HX) 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 RECOMMEND TO TIE TO GND 106 105 GND TDO TRST I/O111 I/O110 I/O109 I/O108 I/O107 I/O106 I/O105 I/O104 VCC GND I/O103 I/O102 I/O101 I/O100 I/O99 I/O98 I/O97 I/O96 I11 GND VCC VCC GND GND VCC VCC GND I10 I9 I/O95 I/O94 I/O93 I/O92 I/O91 I/O90 I/O89 I/O88 GND VCC I/O87 I/O86 I/O85 I/O84 I/O83 I/O82 I/O81 I/O80 ENABLE GND
GND I/O15 I/O14 I/O13 I/O12 I/O11 I/O10 I/O9 I/O8 GND VCC I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 I1 I0 CLK0 VCC GND GND VCC VCC GND GND VCC CLK3 I13 I12 I/O127 I/O126 I/O125 I/O124 I/O123 I/O122 I/O121 I/O120 VCC GND I/O119 I/O118 I/O117 I/O116 I/O115 I/O114 I/O113 I/O112 GND
O0 O1 O2 O3 O4 O5 O6 O7
B7 B6 B5 B4 B3 B2 B1 B0
A7 A6 A5 A4 A3 A2 A1 A0
P0 P1 P2 P3 P4 P5 P6 P7
N7 N6 N5 N4 N3 N2 N1 N0
PIN DESIGNATIONS CLK GND I I/O N/C VCC TDI TCK TMS TDO TRST ENABLE = = = = = = = = = = = = Clock Ground Input Input/Output No Connect Supply Voltage Test Data In Test Clock Test Mode Select Test Data Out Test Reset Program
M7 M6 M5 M4 M3 M2 M1 M0
C
7
L0 L1 L2 L3 L4 L5 L6 L7
K0 K1 K2 K3 K4 K5 K6 K7
G7 G6 G5 G4 G3 G2 G1 G0
H7 H6 H5 H4 H3 H2 H1 H0
J0 J1 J2 J3 J4 J5 J6 J7
I0 I1 I2 I3 I4 I5 I6 I7
GND I/O48 I/O49 I/O50 I/O51 I/O52 I/O53 I/O54 I/O55 GND VCC I/O56 I/O57 I/O58 I/O59 I/O60 I/O61 I/O62 I/O63 I5 I6 CLK1 VCC GND GND VCC VCC GND GND VCC CLK2 I7 I8 I/O64 I/O66 I/O66 I/O67 I/O68 I/O69 I/O70 I/O71 VCC GND I/O72 I/O73 I/O74 I/O75 I/O76 I/O77 I/O78 I/O79 GND
53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104
17466G-044
17466H-066
44
MACH 4 Family
256-BALL BGA CONNECTION DIAGRAM (M4(LV)-256/128)
Bottom View
256-Ball BGA
20 A GND
19 N/C I/O113 O6 N/C I/O117 O2 I/O119 O0 I/O122 P5 I/O125 P2 I/O127 P0 N/C CLK3
18 GND
17 I/O108 N4 I/O109 N5 TRST
16 I/O105 N1 I/O106 N2 I/O111 N7 VCC
15 GND I/O103 M7 I/O107 N3 I/O110 N6
14 I/O100 M4 I/O102 M6 I/O104 N0 VCC
13 I/O96 M0 I/O98 M2 I/O101 M5 N/C
12 GND
11 GND
10 GND
9 GND
8 I/O95 L0 I/O93 L2 I/O90 L5 N/C
7 I/O91 L4 I/O89 L6 I/O86 K1 VCC
6 GND I/O88 L7 I/O84 K3 I/O81 K6
5 I/O87 K0 I/O85 K2 I/O80 K7 VCC
4 N/C I/O83 K6 ENABLE
3 GND I/O82 K5 VCC I/O79 J7 I/O77 J5 I/O73 J1 I/O70 I6 I/O66 I2 N/C N/C
2 GND
1 GND A
B C
GND I/O116 O3 I/O120 P7 I/O123 P4 GND
N/C VCC I/O112 O7 I/O114 O5 I/O118 O1 I/O121 P6 I/O126 P1 N/C N/C
N/C I/O97 M1 I/O99 M3
I11 N/C
N/C I10
N/C I/O94 L1 I/O92 L3
N/C I/O78 J6 I/O75 J3 I/O72 J0 I/O69 I5 I/O65 I1 I/O64 I0 N/C CLK2
GND I/O74 J2 I/O71 I7 I/O68 I4 GND
B C
D E F
VCC TDI I/O115 O4 VCC I/O124 P3 I13 N/C
N/C
I9
VCC TDO I/O76 J4 VCC I/O67 I3 I7 N/C
D E F
G H
I12 GND
PIN DESIGNATIONS CLK GND I I/O N/C VCC TDI TCK TMS TDO TRST ENABLE = = = = = = = = = = = = Clock Ground Input Input/Output No Connect Supply Voltage Test Data In Test Clock Test Mode Select Test Data Out Test Reset Program
I8 GND
G H
J K
N/C GND
N/C N/C
J K
L
N/C
CLK0
N/C
N/C
N/C
N/C
CLK1 I/O63 H0 I/O59 H4 I/O58 H5 I/O56 H7 I/O55 G0 I/O53 G2 I/O52 G3 I/O49 G6 N/C 2
GND I/O62 H1 GND I5 GND
L
M
N/C
N/C I/O0 A0 I/O1 A1 I/O5 A5 I/O8 B0 I/O11 B3 I/O13 B5 I/O14 B6 GND 19
N/C I/O2 A2 I/O6 A6 I/O9 B1 I/O12 B4 I/O15 B7 VCC
I0 I/O3 A3 VCC N/C
C
7 I/O Cell (0-7) PAL Block (A-P)
I6 I/O60 H3 VCC I/O51 G4 TMS
N/C I/O61 H2 I/O57 H6 I/O54 G1 I/O50 G5 I/O48 G7 VCC
M
N P R
GND I1 GND I/O4 A4 I/O7 A7 I/O10 B2 GND
N P R
T
TCK I/O18 C5 I/O21 C2 I/O22 C1 GND 15 I/O24 D7 I/O27 D4 I/O28 D3 I/O30 D1 13 I/O29 D2 I/O31 D0 N/C I/O35 E3 I/O33 E1 N/C
N/C
T
U V
VCC I/O16 C7 N/C
VCC I/O17 C6 I/O19 C4 I/O20 C3 16
VCC I/O23 C0 I/O25 D6 I/O26 D5 14
I2 I3
N/C N/C
N/C I/O37 E5 I/O34 E2 I/O32 E0 8
VCC I/O41 F1 I/O38 E6 I/O36 E4 7
N/C I/O43 F3 I/O39 E7 GND 6
VCC I/O46 F6 I/O42 F2 I/O40 F0 5
VCC I/O47 F7 I/O45 F5 I/O44 F4 4
N/C N/C
U V
W
N/C
N/C
I4
N/C
GND
W
Y
GND 20
GND 18
N/C 17
GND 12
GND 11
GND 10
GND 9
GND 3
GND 1
Y
17466G-045
MACH 4 Family
45
MACH 4 PRODUCT ORDERING INFORMATION
MACH 4 Devices Commercial & Industrial - 3.3V and 5V
Lattice/Vantis programmable logic products are available with several ordering options. The order number (Valid Combination) is formed by a combination of:
M4256 / 128 -7 Y C
FAMILY TYPE M4- = MACH 4 Family (5-V VCC) M4LV- = MACH 4 Family Low Voltage (3.3-V VCC) MACROCELL DENSITY 32 = 32 Macrocells 128N = 128 Macrocells, Non-ISP 64 = 64 Macrocells 192 = 192 Macrocells 96 = 96 Macrocells 256 = 256 Macrocells 128 = 128 Macrocells I/Os /32 /48 /64 /96 /128
48
= 48-pin TQFP for M4(LV)-32/32 or M4(LV)-64/32
OPERATING CONDITIONS C = Commercial (0C to +70C) I = Industrial (-40C to +85C) PACKAGE TYPE A = Ball Grid Array (BGA) J = Plastic Leaded Chip Carrier (PLCC) V = Thin Quad Flat Pack (TQFP) Y = Plastic Quad Flat Pack (PQFP) SPEED -7 = 7.5 ns tPD -10 = 10 ns tPD -12 = 12 ns tPD -14 = 14 ns tPD -15 = 15 ns tPD -18 = 18 ns tPD Valid Combinations
= = = = =
32 I/Os in 44-pin PLCC, 44-pin TQFP or 48-pin TQFP 48 I/Os in 100-pin TQFP 64 I/Os in 84-pin PLCC, 100-pin PQFP or 100-pin TQFP 96 I/Os in 144-pin TQFP 128 I/Os in 208-pin PQFP or 256-ball BGA
Valid Combinations M4-32/32 M4LV-32/32 M4-64/32 M4LV-64/32 M4-96/48 M4LV-96/48 M4-128/64 M4LV-128/64 M4-128N/64 M4LV-128N/64 M4-192/96 M4LV-192/96 M4-256/128 M4LV-256/128 JC, VC, VC48 JC, VC, VC48 JC, VC, VC48 JC, VC, VC48 VC VC YC, VC YC, VC JC JC VC VC YC, AC YC, AC M4-32/32 M4LV-32/32 M4-64/32 M4LV-64/32 M4-96/48 M4LV-96/48 M4-128/64 M4LV-128/64 M4-128N/64 M4LV-128N/64 M4-192/96 M4LV-192/96 M4-256/128 M4LV-256/128
-7, -10, -12, -15
-10, -12, -14, -18
JI, VI, VI48 JI, VI, VI48 JI, VI, VI48 JI, VI, VI48 VI VI YI, VI YI, VI JI JI VI VI YI, AI YI, AI
All MACH devices are dual-marked with both Commercial and Industrial grades. The Industrial speed grade is slower, i.e., M4-256/128-7YC-10YI
Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local Lattice sales office to confirm availability of specific valid combinations and to check on newly released combinations.
46
MACH 4 Family

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